Semiconductor memory devices typically include sense amplifier circuits for amplifying weak data signals from selected memory cells accessed in a read and/or write operation. In addition, sense amplifiers can also “refresh” data values by refreshing memory cell storage capacitor states in the case of memory devices that include dynamic memory cells, such as dynamic random access memories (DRAMs) and/or some types of pseudo static RAMs (PSRAMs).
An increasingly important feature of many DRAMs or other memory products, such as a one transistor (1-T) PSRAMs (one transistor used as a storage element where the product as a whole emulates a static type RAM), can be the ability to operate in low power and/or low voltage environments, such as those of battery powered systems.
As an operating voltage is decreased, the power consumed by a memory chip can also decrease. However, lowering the operating voltage of a 1T PSRAM, for example, can have drawbacks as the lower operating voltage approaches the threshold voltage (Vt) of transistors (e.g., MOSFETs) on the device. For example, the operation of the 1T PSRAM sense amplifier in a low voltage environment, specifically at colder temperatures, can result in higher operating transistor Vts. Such a higher Vts can cause sensing operation “stalls”. Such sensing operation stalls can result in access and/or functional fails.
To better understand various aspects of the disclosed embodiments, a conventional memory device will now be described with reference to FIGS. 6 and 7. FIG. 6 is a schematic diagram of a conventional DRAM sense amplifier arrangement. FIG. 7 is a waveform showing the operation of the sense amplifier arrangement of FIG. 6.
The conventional circuit of FIG. 6 is designated by the general reference character 600 and shows a sense amplifier shared between adjacent array blocks. For example, a sense amplifier may be shared between an active array block and an inactive array block. The conventional sense amplifier arrangement includes a sense amplifier 602, an equalization circuit 604, a first access circuit 606, a second access circuit 608, and a first array block 610. It is understood that a second array block (not shown) could be connected to second access circuit 608.
A sensing operation will now be described with reference to FIG. 6 in conjunction with FIG. 7. For purposes of this discussion it will be assumed that memory cell 612-1 within first array block 610 is being accessed in a read operation.
Prior to memory cell 612-1 being accessed, bitline pair (BLt<0> and BLc<0>) can be precharged to about ½ of a bitline high voltage (e.g., to a regulated level “vbleq”). This is shown in FIG. 7 by bitlines Blt and Blc being at the equalization voltage vbleq.
During a sense operation, a word line (e.g., WL<1>) can be driven high. As a result, a transistor M1 within memory cell 612-1 can be turned on, transferring charge from the corresponding storage capacitor C1, to a bitline (BLc<0>). More particularly, when word line WL<0> goes high, by operation of transistor M1, capacitor C1 “charge shares” with BLc<0>. Thus, charge on the active bitline (in this case BLc<0>) is shared with the stored cell charge (in this case, charge on capacitor C1). As a result, the potential on the active bitline can change.
At the same time, the other bitline in the pair (in this case bit line BLt<0>), known as the “reference” bitline, can maintain a precharge state of about ½ the bitline high voltage level (e.g., vbleq). In this way, an initial differential voltage can develop between the bitline pair (e.g., the bitlines can “split”). This is shown in FIG. 7 by waveform BLc falling below the equalization voltage vbleq, while waveform Blt remains at the equalization voltage vbleq.
Of course, when a memory cell of an adjacent column is accessed, bitline BLt<0> will be the active bit line, while bitline BLc<0> will be the reference bitline.
Once a sufficient differential bitline voltage has been established, the sense amplifier 602 can be set or enabled. When sense amplifier 602 is set, the differential voltage of the bitline pair, known as the “signal,” can be amplified and latched. In this way, a data value can be read from a memory cell.
In the conventional sense amplifier arrangement illustrated by FIGS. 6 and 7, the sense amplifier 602 can be “set” or enabled by driving of sources of cross-coupled transistors within the sense amplifier 602. More particularly, sense amplifier 602 can include cross-coupled n-channel (e.g., NMOS) transistors N1 and N2, and cross-coupled p-channel (e.g., PMOS) transistors P1 and P2. Transistors N1 and N2 may have commonly connected sources that receive a signal “setn”. In a similar fashion, transistors P1 and P2 may have commonly connected sources that receive a signal “setp”.
Prior to sense amplifier 602 being set, set signals (setn and setp), can be precharged at, or about, the equalization voltage vbleq. In a set operation (i.e., during a sense amplifier enable period), set signal setn can be driven to ground while set signal setp can be driven to a bitline high voltage. This is shown in detail in the waveforms of FIG. 7.
It is noted that in the case of read and/or refresh operation, a sense amplifier 602 can also “writeback” the sensed logic level, thereby enabling the storage capacitor to retain the stored data value. That is, if the memory cell stored a logic “0”, the capacitor is discharged to retain a discharged state. Conversely, if the memory cell stored a logic “1”, the capacitor is charged to retain a charged state.
At supply voltage levels substantially higher than the threshold voltages of the devices within the sense amplifier 602, the transistors (P1, P2, N1 and N2) can have a sufficient gate-to-source voltage to quickly drive the bitline pair to complementary values (i.e., bitline high voltage and ground).
However, at lower power supply voltages, sense amplifiers can suffer from performance drawbacks, particularly at lower operating temperatures. One such drawback will now be described in more detail.
Referring still to FIGS. 6 and 7, it will be assumed that an accessed memory cell (e.g., 612-1) stores a logic “0”. When sense amplifier 602 tries to amplify a resulting logic “0” signal, n-channel devices (N1 and N2) can have very little overdrive in trying to drive their respective bitlines. In a sense operation, one transistor of each cross-coupled pair can be considered an “on-side” conduction transistor. An on-side conduction n-channel transistor can pull a lower potential bitline (with respect to the other bitline) to ground, while an on-side conduction p-channel transistor can pull the other bitline to a bitline high voltage.
In particular, when a logic “0” data signal is on bitline Blc<0>, bitline Blt<0> will have a higher potential, and provide such a potential to a gate of transistor N2. Thus, transistor N2 is an onside conduction transistor in this case. However, the conduction of onside transistor N2 can be limited as its gate-to-source voltage (Vgs) can be about vbleq, particularly at lower power supply voltages, and voltage vbleq can be scaled according to a power supply voltage. Thus, the overdrive of an on-side conduction transistor can be limited. In this same example, transistor N1 will be an “off-side” conduction transistor. The Vgs of transistor N1 in this case can be the difference between vbleq and the signal on the bitline (i.e., vbleq-signal).
Reduced overdrive in transistors can be exacerbated not only by lower operating voltage, but by lower operating temperature as well.
PSRAM devices, which can include DRAM type sensing schemes like that of FIGS. 6 and 7, can have relatively low operating temperature specifications. As but one example, a PSRAM cold temperature operating specification can be −25° C. to −40° C. At such lower temperature, a threshold voltage (Vt) of an n-channel transistor can increase. As a result, within a sense amplifier, an on-side conduction n-channel device may have a reduced overdrive capability. This can result in an undesirable situation referred to as sense amplifier “stall.”
In a sense amplifier stall, a bitline that should be driven to ground at a relatively rapid rate, is driven slower than desired, due to the reduction in overdrive of the on-side n-channel device. A sense amplifier stall is illustrated by portion 700 in FIG. 7. As shown, unlike high-going bitline Blt, which rises at a relatively fast rate to a high bitline voltage VCC, low-going bit line Blc falls a relatively slow rate to ground.
Sense amplifier stall can result in access or functional failures, depending on the severity of the stall.
In light of the above, it would be desirable to arrive at some sense amplifier arrangement and/or control method that would allow for effective amplifier operation at low voltage and/or low temperature conditions.